Semiconductor storage device

ABSTRACT

A voltage of a bit line connected to a memory cell is stepped up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor storage devicecomprising a memory cell, a bit line connected to the memory cell, aprecharge circuit which steps up a voltage of the bit line up to a powersupply voltage, and a step-down circuit which steps down the voltage ofthe bit line to a voltage level lower than the power supply voltagebefore data is read from the memory cell.

2. Description of the Related Art

In the field of a semiconductor storage device, there is a conventionaltechnology for improving a data reading speed by stepping down a bitline precharged with a power supply voltage to a voltage level lowerthan the power supply voltage before data is read so that the powersupply voltage level in the bit line can change to a ground levelsooner. The change from the power supply voltage level to the groundlevel in the bit line is detected by a PMO transistor at a subsequentgate. However, when a step-down level in the bit line is below anoperation region of a transistor for detection, through current and adata-read error may occur. A similar data-read error also occur in thecase where a sense amplifier or a PMOS cross driver is connected to thebit line. Therefore, it is necessary to keep a step-down level of thebit line around a threshold voltage of the PMOS transistor.

In a SRAM circuit where the bit line is precharged with the power supplyvoltage, charges of the power supply voltage level of the bit line flowinto a node at which “L” data of SRAM is retained as soon as a word lineis activated, in a non-selected column in which reading or writing isbeing performed. The inflow of too many charges at the time results inthe generation of a data-write error. An indicator called a static noisemargin shows a level of resistance against the data-write error. Thestatic noise margin has been reduced in recent years as thesemiconductor is increasingly miniaturized, and the data-write error ismore likely to occur. In order to respond to the recent trend, there isa technology wherein a potential of the power supply voltage level ofthe bit line is stepped down so as to reduce the current flow into thenode of the memory cell at which “L” data is stored when the word lineis activated. When the voltage step-down level in the bit line at thattime is not enough, the data-write error occurs due to the reasondescribed above. When the voltage step-down level in the bit line isexcessive, an data-write error is caused by charges of “L” level of thebit line which flow into the node at which “H” data of the SRAM isretained. Therefore, it is necessary to step down the voltage of the bitline to such a voltage level that can assure the static noise margin.

Below is described a technology for stepping down the voltage of the bitline in a conventional semiconductor storage device referring to FIGS.7A and 7B. FIG. 7A is a circuit diagram illustrating a constitution of aconventional semiconductor storage device, and FIG. 7B is a timing chartillustrating an operation of the semiconductor storage device. In FIG.7A, 11 denotes a SRAM memory cell, 12 denotes a precharge circuit, 13denotes an equalizing circuit, 14 denotes a reading circuit, 15 denotesa step-down circuit, BL and /BL are complementary bit lines, WL denotesa word line, PC denotes a precharge control signal, DEC denotes astep-down/equalizing control signal, QP31, QP32 and QP33 denote PMOStransistors constituting the precharge circuit 12, QP34 denotes a PMOStransistor constituting the equalizing circuit 13, QN31 and QN32 denoteNMOS transistors constituting the step-down circuit 15, and Inv0 denotesan inverter.

The step-down circuit 15 comprising the step-down transistors QN31 andQN32 is additionally provided in order to step-down voltages of the bitlines BL and /BL prior to the activation of the word line WL. Sources ofthe step-down transistors QN31 and QN32 are connected to the ground,drains thereof are directly connected to the bit lines BL and /BL, andgates thereof are connected to a gate of the equalizing transistor QP34via the inverter Inv0. The gates of the step-down transistors QN31 andQN32 are driven by the step-down/equalizing control signal DEC.

As shown in FIG. 7B, prior to the activation of the word line WL, theprecharge control signal PC is negated and turns to “H” level at atiming t31, the precharge transistors QP31 and QP32 and the equalizingtransistor QP33 are turned off, which leaves the bit lines BL and /BL ina floating state.

At a timing t32, the step-down/equalizing control signal DEC is assertedand turns to “H” level, and the step-down transistors QN31 and QN32 inthe step-down circuit 15 are turned on. Further, the equalizingtransistor QP34 in the equalizing circuit 13 is turned on, charges ofthe bit line BL and /BL are then discharged, and potentials of the bitlines BL and /BL are stepped down to a predetermined voltage level. Apossible example of the predetermined voltage level is VDD-Vth. VDD is apower supply voltage used for the precharge, and Vth is a thresholdvoltage of the MOS transistors.

When the step-down/equalizing control signal DEC is negated and turns to“L” level at a timing t33, the step-down transistors QN31 and QN32 areturned off, and the equalizing transistor QP34 is turned off. As aresult, the step-down and equalizing operations for the bit lines BL and/BL are halted.

At a timing t34, the word line WL is asserted, and data is read from thememory cell 11. In the case where “0” is stored in the memory cell 11,current flows from the bit line BL into the memory cell 11, and thepotential of the bit line BL is lowered; however, the potential of thecomplementary bit line /BL is not stepped down. The state in which thebit line BL=“L” level and the complementary bit line /BL=“H” level isjudged by the reading circuit 14 as “0” data. In the case where “1” isstored in the memory cell 11, the current flows from the complementarybit line /BL into the memory cell 11, and the potential of thecomplementary bit line /BL is lowered, however, the potential of the bitline BL is not stepped down. The bit line BL=“H” level and thecomplementary bit line /BL=“L” level is judged by the reading circuit 14as “1” data. Broken lines denoting the potentials of the bit lines BLand /BL illustrate the potential reduction irrespective of whether thereduction occurs in the bit line BL or the complementary bit line /BL.

At a timing t35, the word line WL is at “L” level, and the data readingoperation is terminated. At a timing t36, the precharge control signalPC is asserted and turns to “L” level, and the precharge transistorsQP31 and QP32 and the equalizing transistor QP33 are turned on. Then,the bit lines BL and /BL are precharged with the power supply voltage.

In the foregoing description, the step-down levels of the bit lines BLand /BL are adjusted in accordance with a pulse width of thestep-down/equalizing control signal DEC. Provided that the step-downlevel is ΔV, and the pulse width of the step-down/equalizing controlsignal DEC is Tw, ΔV∝Tw, which means that the step-down level ΔV issubstantially in proportion with the pulse width Tw of thestep-down/equalizing control signal DEC.

In the conventional technology, since the step-down transistors QN31 andQN32 of the step-down circuit 15 are directly connected to the bit linesBL and /BL, load capacities of the bit lines BL and /BL are increased,which results in the deterioration of a reading time in a data cycle ofreading data from the memory cell.

Further, a timing of the termination of the step-down control is likelyto vary when the load capacities of the bit lines BL and /BL areincreased. As a result, the step-down levels of the bit lines BL and /BLalso vary, which may result in a data-read error.

SUMMARY OF THE INVENTION

Therefore, a main object of the present invention is to provide asemiconductor storage device capable of reliably preventing thedeterioration of a reading speed at the time when data is read from amemory cell by providing a bit line with a step-down circuit without anyincrease of a load capacity of the bit line, and capable of unfailinglypreventing a data-read error by executing a stable step-down control.

In order to solve the foregoing problems, a semiconductor storage deviceaccording to the present invention comprises

-   -   a memory cell;    -   a bit line connected to the memory cell;    -   a precharge circuit for stepping up a voltage of the bit line to        a power supply voltage;    -   a step-down circuit for stepping down the voltage of the bit        line to a voltage level lower than the power supply voltage        before data is read from the memory cell;    -   a high-potential-side power supply and a low-potential-side        power supply respectively connected to the precharge circuit;        and    -   a precharge switching element for controlling a connection        between the high-potential-side power supply and the precharge        circuit and a connection between the low-potential-side power        supply and the precharge circuit, wherein    -   a power supply connecting circuit is provided between the        precharge switching element and the high-potential-side power        supply, and    -   a ground connecting circuit is provided between a connecting        point at which the precharge switching element is connected to        the power supply connecting circuit and the low-potential-side        power supply.

The present invention exerts the following effect. When the prechargecircuit is in assert state, the step-down circuit is in negate state.When the step-down circuit is in assert state, the precharge circuit isin negate state. Thus, the precharge circuit and the step-down circuitare in the trade-off relationship in their operation states. In thepresent invention wherein the relationship is utilized, the prechargecircuit is interposed between the step-down circuit and the bit linewhen the step-down circuit is connected to the bit line. Morespecifically, the precharge switching element which is turned on at thetime of the precharge is provided in the precharge circuit, and one endof the precharge switching element is connected to the bit line, whilethe other end thereof is connected to the high-potential-side powersupply. Then, the power supply connecting circuit is interposed betweenthe precharge switching element and the high-potential-side power supplyso that the precharge switching element and the high-potential-sidepower supply are not constantly connected to each other. Further, theconnecting point at which the precharge switching element and the powersupply connecting circuit are connected to each other is used as acontrol node, and the ground connecting circuit is interposed betweenthe control node and the low-potential-side power supply. Accordingly,the control node and the low-potential-side power supply are notconstantly connected to each other. The power supply connecting circuitis interposed between the control node and the high-potential-side powersupply. The ground connecting circuit is interposed between the controlnode and the low-potential-side power supply so that thehigh-potential-side power supply and the low-potential-side power supplywill not be electrically short-circuited to each other. The power supplyconnecting circuit and the ground connecting circuit are turned on andoff in the trade-off manner.

At the time of the precharge, the power supply connecting circuit isturned on while the ground connecting circuit is kept in the OFFposition. Accordingly, the bit line is connected to thehigh-potential-side power supply via the control node and the powersupply connecting circuit, and the bit line is thereby precharged. Atthe time, the precharge switching element is ON.

In the step-down operation, the power supply connecting circuit isturned off, and the ground connecting circuit is turned on. Accordingly,the bit line is connected to the low-potential-side power supply via thecontrol node and the ground connecting circuit, and the voltage of thebit line is stepped down. At the time, the precharge switching elementis ON.

As described, the ground connecting circuit constituting the step-downcircuit is connected to the node (control node) of the prechargeswitching element on the side of the high-potential-side power supply(side of the power supply connecting circuit). The ground connectingcircuit is not directly connected to the bit line. The prechargeswitching element is interposed between the ground connecting circuitand the bit line. Accordingly, a load capacity of the bit line isprevented from increasing. As a result, it becomes possible to shortenthe time which requires for carrying out charge and discharge of the bitline at the time of data read. Thereby, the data reading speed improves.

In the semiconductor storage device thus constituted, the power supplyconnecting circuit and the ground connecting circuit may be integrallyconstituted as an inverter which is turned on and off by a commonprecharge/step-down control signal. Because the precharge/step-downcontrol signal serves as a control signal of the power supply connectingcircuit and a control signal of the ground connecting circuit, an areareduction can be improved. Further, there are the following advantages:The on-off control of the power supply connecting circuit and the on-offcontrol of the ground connecting circuit can be performed at the sametime, which makes it difficult for through current to flow; and theinfluence of setup on input signals in the precharge circuit and thestep-down circuit can be lessened because the precharge/step-downcontrol signal serves as a control signal of the precharge circuit and acontrol signal of the step-down circuit.

In the semiconductor storage device thus constituted, the power supplyconnecting circuit and the ground connecting circuit may be equallyconnected to a group of bit lines for a plurality of columnscorresponding to memory cells for a plurality of columns. Thusconstituted, the sharing of the constituent elements can be realized,and a layout size can be largely reduced.

According to the present invention, the load capacity of the bit linecan be prevented from increasing. Further, the speed at which the datais read from the memory cell can be prevented from deteriorating, anddata-read errors can be reliably prevented from happening.

The technology according to the present invention can control theincrease of the load capacity of the bit line and prevent the speed atwhich the data is read from the memory cell from deteriorating.Therefore, the technology is advantageously applied to a semiconductorstorage device such as SRAM for which a higher reading speed is stronglydemanded.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects as well as advantages of the invention willbecome clear by the following description of preferred embodiments ofthe invention and be specified in the claims attached hereto. A numberof benefits not recited in this specification will come to the attentionof the skilled in the art upon the implementation of the presentinvention.

FIG. 1 is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 1 ofthe present invention.

FIG. 2 is a circuit diagram specifically illustrating a power supplyconnecting circuit and a ground connecting circuit according to thepreferred embodiment 1.

FIG. 3 is a timing chart illustrating an operation of the semiconductorstorage device according to the preferred embodiment 1.

FIG. 4A is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 2 ofthe present invention.

FIG. 4B is a timing chart illustrating an operation of the semiconductorstorage device according to the preferred embodiment 2.

FIG. 5 is a circuit diagram illustrating an equivalent circuit accordingto the preferred embodiment 2.

FIG. 6 is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 3 ofthe present invention.

FIG. 7A is a circuit diagram illustrating a constitution of asemiconductor storage device according to the conventional technology.

FIG. 7B is a timing chart illustrating an operation used in theconventional technology.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, preferred embodiments of the present invention aredescribed referring to the drawings.

Preferred Embodiment 1

FIG. 1 is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 1 ofthe present invention. Bit lines BL and /BL are connected to sources ofa pair of access transistors in a memory cell 1 of SRAM (Static RandomAccess Memory) activated by access from a word line WL. A prechargecircuit 2, an equalizing circuit 3 and a reading circuit 4 are connectedto the bit lines BL and /BL. The equalizing circuit 3 comprises anequalizing transistor QP3. A PMOS transistor constitutes the equalizingtransistor QP3. A source and a drain of the equalizing transistor QP3are connected to the bit lines BL and /BL, and an equalizing controlsignal EQ is applied to a gate thereof. The precharge circuit 2comprises switching transistors QP1 and QP2, which are PMOS transistorsserving as precharge switching elements, and a power supply connectingcircuit 5. A ground connecting circuit 6, which is a step-down circuit,is connected to the bit lines BL and /BL with the precharge circuit 2interposed therebetween. A source of the precharge transistor QP1 isconnected to the bit line BL, and a source of the precharge transistorQP2 is connected to the bit line /BL. A gate of the precharge transistorQP1 and a gate of the precharge transistor QP2 are connected to eachother, and further connected to the gate of the equalizing transistorQP3. A drain of the precharge transistor QP1 and a drain of theprecharge transistor QP2 are connected to each other, thereby serving asa control node Nc. The control node Nc is connected to ahigh-potential-side power supply (VDD) via the power supply connectingcircuit 5, and further connected to a low-potential-side power supply(GND) via the ground connecting circuit 6. The power supply connectingcircuit 5 is turned on and off by a precharge control signal PC tothereby connect/disconnect the control node Nc with respect to thehigh-potential-side power supply. The ground connecting circuit 6 isturned on and off by a step-down control signal DC to therebyconnect/disconnect the control node Nc with respect to thelow-potential-side power supply. The ON-OFF control by the power supplyconnecting circuit 5 and the ON-OFF control by the ground connectingcircuit 6 are related to each other in a trade-off manner.

The ground connecting circuit 6 constitutes a main constituent of astep-down function. The main constituent of the step-down function isnot directly connected to the bit lines BL and /BL, but is connected tothe bit lines BL and /BL with the switching transistors QP1 and QP2interposed therebetween. The present invention is characterized in thatthe main constituent of the step-down function is thus provided in thebit lines BL and /BL with the switching transistors QP1 and QP2interposed therebetween. Because of the constitution thus described,load capacities of the bit lines BL and /BL can be prevented fromincreasing.

FIG. 2 is a circuit diagram specifically illustrating the power supplyconnecting circuit 5 and the ground connecting circuit 6 shown inFIG. 1. A PMOS precharge transistor QP0 constitutes the power supplyconnecting circuit 5, and an NMOS step-down transistor QN0 constitutesthe ground connecting circuit 6. A source of the precharge transistorQP0 in the power supply connecting circuit 5 is connected to thehigh-potential-side power supply, a drain thereof is connected to thecontrol node Nc, and the precharge control signal PC is applied to agate thereof. A source of the step-down transistor QN0 in the groundconnecting circuit 6 is connected to the low-potential-side powersupply, a drain thereof is connected to the control node Nc, and thestep-down control signal DC is applied to a gate thereof.

An operation of the semiconductor storage device thus constitutedaccording to the present preferred embodiment is described referring toa timing chart shown in FIG. 3. At a timing t0, the low-active prechargecontrol signal PC is in assert state, the step-down control signal DC isin negate state, and the low-active equalizing control signal EQ is inassert state. Because the precharge control signal PC is at “L” level,the precharge transistor QP0 is in the ON state, and a potential of thecontrol node Nc is the power supply voltage VDD. Further, the equalizingcontrol signal EQ is at “L” level; therefore, the switching transistorsQP1 and QP2 and the equalizing transistor QP3 is in the ON state.Accordingly, the power supply voltage VDD of the control node Nc isapplied to the bit lines BL and /BL, and the bit lines BL and /BL arethereby precharged.

Prior to the activation of the word line WL (t3), at a timing t1, theprecharge control signal PC is negated to turn to “H” level, and theprecharge transistor QP0 is thereby turned off. Then, the control nodeNc is disconnected from the power supply voltage VDD, which leaves thebit lines BL and /BL in a floating state. At the time, the switchingtransistors QP1 and QP2 remain in the ON state.

At a timing t2, the step-down control signal DC is asserted to turn to“H” level. Then, the step-down transistor QN0 in the OFF state so far isturned on, and a potential of the control node Nc is stepped down to theground level. Because the switching transistors QP1 and QP2 are in theON state at the time, the voltages of the bit lines BL and /BL arestepped down in response to the potential drop in the control node Nc.The potentials of the bit lines BL and /BL are stepped down along with acertain time constant and to a predetermined voltage level. A possibleexample of the predetermined voltage level is VDD-Vth. Vth is athreshold voltage of the MOS transistors. At the time, a step-down speedin the bit line is lower as the voltage is closer to the predeterminedvoltage. Therefore, variability in a time length from the time when thestep-down transistor QN0 is turned on to the time when the switchingtransistors QP1 and QP2 are turned on and variability in the step-downlevel resulting from the characteristic variability of the step-downtransistor QN0 can be controlled.

At a timing t3, the equalizing control signal EQ is negated to turn to“H” level. At the time, the switching transistors QP1 and QP2 are turnedoff, and the step-down transistor QN0 is thereby completely disconnectedfrom the bit lines. Immediately after that, the word line WL isactivated to turn to “H” level. When the equalizing control signal EQturns to at “H” level, the switching transistors QP1 and QP2 are turnedoff and thereby disconnected from the ground, which stops the step-downoperation for the bit lines BL and /BL. Further, the equalizingtransistor QP3 is turned off, which stops the equalizing operation forthe bit lines BL and /BL. Since the word line WL is at “H” level, datais read from the memory cell 1. The reading operation at the time issimilar to that of the conventional technology.

According to the present preferred embodiment, the step-down transistorQN0, which is the main constituent of the step-down function, is notdirectly connected to the bit lines BL and /BL, and the switchingtransistors QP1 and QP2 are interposed therebetween. Accordingly, theload capacities of the bit lines BL and /BL can be prevented fromincreasing. Further, during the reading operation, the time constantused when the bit lines BL and /BL shift from the power supply voltageVDD to the ground level is lessened so that the data can be read at ahigh speed. Provided that an amount of time necessary for the data readin the conventional technology is Tu and an amount of time necessary forthe data read according to the present invention is Ta, Ta<Tu.

The PMOS transistors are used as the switching transistors QP1 and QP2.Accordingly, during the step-down operation, when the voltages of thebit lines BL and /BL are stepped down, source-drain voltages in theswitching transistors QP1 and QP2 are reduced, and the step-downcapacities of the PMOS transistors QP1 and QP2 are lessened. As aresult, variability of the step-down levels in the bit lines can beeffectively alleviated in the case where a timing of terminating thestep-down control varies.

Preferred Embodiment 2

FIG. 4A is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 2 ofthe present invention. FIG. 5 is a circuit diagram illustrating anequivalent circuit shown in FIG. 4A. The gate of the prechargetransistor QP0 and the gate of the step-down transistor QN0 areconnected to each other, and these transistors QP0 and QN0 constitute aninverter Inv. The precharge transistor QP0 and the step-down transistorQN0 are controlled by a precharge/step-down control signal PDC which isa control signal common to them.

An operation of the semiconductor storage device thus constitutedaccording to the present preferred embodiment is described referring toa timing chart shown in FIG. 4B. At a timing t10, theprecharge/step-down control signal PDC is at “L” level, and thelow-active equalizing control signal EQ is in assert state. Because theprecharge/step-down control signal PDC is at “L” level, the prechargetransistor QP0 is in the ON state, while the step-down transistor QN0 isin the OFF state, and the potential of the control node Nc isaccordingly the power supply voltage VDD. Because the equalizing controlsignal EQ is at “L” level, the switching transistors QP1 and QP2 and theequalizing transistor QP3 is in the ON state. Accordingly, the powersupply voltage VDD of the control node Nc is applied to the bit lines BLand /BL, and the bit lines BL and /BL are precharged.

Prior to the activation of the word line WL (t12), at a timing t11, theprecharge/step-down control signal PDC turns to “H” level, and as soonas the precharge transistor QP0 is turned off, the step-down transistorQN0 is turned on. Accordingly, the control node Nc is disconnected fromthe power supply voltage VDD and connected to the ground at the sametime. At the time, the switching transistors QP1 and QP2 are in the ONstate; therefore, the voltages of the bit lines BL and /BL are steppeddown in response to the potential drop of the control node Nc. Thepotentials of the bit lines BL and /BL are stepped down along with acertain time constant and to a predetermined voltage level (VDD-Vth).

At a timing t12, the equalizing control signal EQ is negated to turn to“H” level, and the word line WL is activated to turn to “H” level. Whenthe equalizing control signal EQ is at “H” level, the switchingtransistors QP1 and QP2 are turned off, and thereby disconnected fromthe ground, which stops the step-down operation for the bit lines BL and/BL. Further, the equalizing operation for the bit lines BL and /BL alsostops since the equalizing transistor QP3 is turned off. Since the wordline WL is at “H” level, data is read from the memory cell 1.

At a timing t13, the word line WL is at “L” level, and the data readingoperation is terminated. At a timing t14, the precharge/step-downcontrol signal PDC turns to “L” level, and the control node Nc isprecharged with the power supply voltage. At the same time, theequalizing control signal EQ is asserted, and the switching transistorsQP1 and QP2 and the equalizing transistor QP3 are turned on.Accordingly, the bit lines BL and /BL are precharged with the powersupply voltage.

According to the present preferred embodiment, the precharge/step-downcontrol signal PDC is shared for the control signal for the power supplyconnecting circuit 5 (precharge transistor QP0) and the control signalfor the ground connecting circuit 6 (step-down transistor QN0), whichimproves an area reduction. Further, the on-off control of the powersupply connecting circuit 5 and the ground connecting circuit 6 isperformed at the same time. Therefore, variability in the step-downlevel and through current can be controlled even if there is a variationin the timing between the turn-off of the power supply connectingcircuit 5 and the turn-on of the ground connecting circuit 6 or betweenthe turn-on of the power supply connecting circuit 5 and the turn-off ofthe ground connecting circuit 6.

In the preferred embodiment 1, the control signals for the prechargecircuit 2 are the precharge control signal PC and the step-down controlsignal DC. In the present preferred embodiment, however, only theprecharge/step-down control signal PDC is used. As a result, in theprecharge circuit 2, the influence of setup on input signals islessened.

Preferred Embodiment 3

FIG. 6A is a circuit diagram illustrating a constitution of asemiconductor storage device according to a preferred embodiment 3 ofthe present invention. The inverter Inv is connected equally to thecontrol nodes Nc in the precharge circuits 2 provided with the step-downfunction which are provided in a group of bit lines BL and /BL in aplurality of memory cells 1 parallel-arranged in a column direction.More specifically describing the constitution, the power supplyconnecting circuit 5 (precharge transistor QP0), ground connectingcircuit 6 (step-down transistor QN0) and precharge/step-down controlsignal PDC are shared among the group of bit lines BL and /BL. Anoperation according to the present preferred embodiment is similar tothat of the preferred embodiment 2. According to the present preferredembodiment, wherein the constituent elements are shared, a layout sizecan be largely reduced.

While there has been described what is at present considered to bepreferred embodiments of this invention, it will be understood thatvarious modifications may be made therein, and it is intended to coverin the appended claims all such modifications as fall within the truespirit and scope of this invention.

1-4. (canceled)
 5. A semiconductor storage device comprising: a memorycell, a first bit line connected to the memory cell, a precharge circuitfor stepping up a voltage of the first bit line, and a power supplyconnecting circuit for supplying a high-potential-side power to theprecharge circuit, a ground connecting circuit for supplying alow-potential-side power to the precharge circuit, wherein the precharge circuit steps up a voltage of the bit line by supplying thehigh-potential-side power to the first bit line, the precharge circuitsteps down a voltage of the bit line by supplying the low-potential-sidepower to the first bit line, and the precharge circuit comprises a firstPMOS transistor of which source is supplied one of thehigh-potential-side power from the power supply connecting circuit andthe low-potential-side power from the ground connecting circuit, and ofwhich drain supplies one of the high-potential-side power and thelow-potential-side power to the first bit line.
 6. The semiconductorstorage device as claimed in claim 5, further comprises: a second bitline connected to the memory cell, wherein the pre charge circuitfurther comprises a second PMOS transistor of which source is suppliedone of the high-potential-side power from the power supply connectingcircuit and the low-potential-side power from the ground connectingcircuit, and of which drain supplies one of the high-potential-sidepower and the low-potential-aide power to the second bit line.
 7. Thesemiconductor storage device as claimed in claim 6, wherein the memorycell is an SRAM.
 8. The semiconductor storage device as claimed in claim6, wherein the power supply connecting circuit comprises a thirdtransistor of which source is supplied the high-potential-side powerfrom a high potential-side power supply and drain supplies thehigh-potential-side power to the precharge circuit, and the groundconnecting circuit comprises a fourth transistor of which source issupplied the low-potential-side power from a low-potential-side powersupply and drain supplies the low-potential-side power to the prechargecircuit.
 9. The semiconductor storage device as claimed in claim 6,further comprises: an equalizing circuit for equalizing a voltage of thefirst bit line and a voltage of the second bit line.
 10. Thesemiconductor storage device as claimed in claim 9, wherein theequalizing circuit comprises a fifth transistor of which source anddrain are connected to the first bit line and the second bit linerespectively, and gates of the first transistor, the second transistor,and fifth transistor are controlled by a common control signal.